A wide tuning range, 1 GHz-2.5 GHz DLL-based fractional frequency synthesizer

A fractional multiplying delay-locked loop (FMDLL) for high-speed on-chip clock generation applications is presented. The output frequency can be adjusted over 1 GHz to 2.5 GHz with selectable fractional multiplication ratios of M+k/(2N_C) in which N_C could be 3, 4, or 5. Designed in a 0.18 μm digital CMOS technology, the whole synthesizer, including the digital part, dissipates 15.5 mW from a 1.8-V supply at 2.5 GHz output frequency. In the proposed FMDLL architecture, a reference clock signal is injected into the oscillator at certain times, which resets the jitter accumulated during the previous cycles. While the loop filter consists of only a simple capacitor, the settling time is 5 μsec.