A gigahertz wideband CMOS multiplier for UWB transceiver

Author

Zhou, Lei ; Xu, Yong Ping ; Lin, Fujiang

Author_Institution

Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore

fYear

2005

fDate

23-26 May 2005

Firstpage

5087

Abstract

A wideband CMOS differential four-quadrant analog multiplier is described. The multiplier is designed to implement a correlator for ultra wideband (UWB) transceivers. With the dominant pole at the internal node being cancelled, the bandwidth of the multiplier can be increased as much as five times under no load condition. The simulation shows that the bandwidths of the multiplier can be as high as 10 GHz without the load and 7 GHz when loaded by an output buffer. The multiplier is able to operate with a 0.2-ns narrow monocycle pulse. The multiplier is based on a 0.18-μm CMOS process and operates under a 1.8-V supply.

Keywords

CMOS analogue integrated circuits; analogue multipliers; correlators; integrated circuit design; network analysis; poles and zeros; transceivers; ultra wideband communication; 0.18 micron; 0.2 ns; 1.8 V; 7 GHz; UWB transceiver; analog correlator; circuit analysis; circuit design; differential four-quadrant analog multiplier; dominant pole; gigahertz wideband CMOS multiplier; monocycle pulse; output buffer; ultra wideband transceiver; Bandwidth; Correlators; FCC; Linearity; MOSFETs; Microelectronics; Transceivers; Transconductors; Ultra wideband technology; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465778

Filename

1465778