A high-frequency phase-compensation fractional-N frequency synthesizer

Author

Yang, Ching-Yuan ; Chen, Jen-Wen ; Tsai, Meng-Ting

Author_Institution

Dept. of Electr. Eng., Nat. Chung-Hsing Univ., Taichung, Taiwan

fYear

2005

fDate

23-26 May 2005

Firstpage

5091

Abstract

A new type of high-frequency fractional-N frequency divider with a phase compensation technique is developed, which can operate for frequencies ranging from 1 GHz to 2.5 GHz, and achieve a divide ratio of (256-271) + (f/16). The on-chip phase compensation by a delay-locked loop (DLL) is adopted to reduce the fractional spurs in the fractional-N frequency synthesizer. The fractional-N synthesizer is simulated using a 0.35- μm standard CMOS technology and the power dissipation is about 70 mW under the supply voltage of 3.3 V.

Keywords

CMOS analogue integrated circuits; delay lock loops; frequency dividers; frequency synthesizers; integrated circuit design; 0.35 micron; 1 to 2.5 GHz; 3.3 V; CMOS technology; DLL; delay-locked loop; divide ratio; fractional spurs; fractional-N frequency synthesizer; high-frequency fractional-N frequency divider; high-frequency phase-compensation; power dissipation; CMOS technology; Delay; Frequency conversion; Frequency synthesizers; Phase frequency detector; Phase locked loops; Phase noise; Timing; Voltage-controlled oscillators; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465779

Filename

1465779