Title :
Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT
Author :
Cheng, Chih-Chi ; Huang, Chao-Tsung ; Tseng, Po-Chih ; Pan, Chia-Ho ; Chen, Liang-Gee
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
In this paper, a memory-efficient VLSI implementation for line-based 2D DWT, named the multiple-lifting scheme, is proposed. Memory bandwidth and memory size dominate the cost of 2D DWT and are highly related to the total power and area of 2D DWT VLSI implementation, respectively. The proposed multiple-lifting scheme can reduce not only the average memory bandwidth but about 50% area of the line buffer in the 2D DWT module. The corresponding data scan, M-scan, is proposed to achieve the multiple-lifting scheme and eliminate the data buffer as well.
Keywords :
VLSI; buffer storage; discrete wavelet transforms; 2D DWT VLSI implementation; M-scan; average memory bandwidth reduction; data buffer elimination; data scan; line buffer area reduction; line-based 2D DWT; memory-efficient VLSI implementation; multiple-lifting scheme; Bandwidth; Chaos; Computer buffers; Costs; Discrete wavelet transforms; Hardware; Random access memory; Read-write memory; Registers; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1465804
