Title :
Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity
Author :
Darabiha, Ahmad ; Carusone, Anthony Chan ; Kschischang, Frank R.
Author_Institution :
Edward S. Rogers Sr. Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Abstract :
A 3.2-Gbit/sec 2048-bit parallel LDPC decoder is implemented in a 0.18 μm CMOS process. We employ two new techniques to address the interconnect problem: A broadcasting technique reduces the total amount of check-to-variable interconnect wires by more than 40%. A hierarchical placement algorithm places the variable and check nodes in the top-level hierarchy of the design and reduces the maximum wire length by up to 50%.
Keywords :
CMOS logic circuits; decoding; integrated circuit interconnections; integrated circuit layout; parallel processing; parity check codes; 0.18 micron; 2048 bit; 3.2 Gbit/s; CMOS; broadcasting technique; check nodes placement; check-to-variable interconnect wire reduction; hierarchical placement algorithm; low density parity check decoders; maximum wire length reduction; parallel LDPC decoder; random parity-check matrix; reduced interconnect complexity decoders; variable nodes placement; Algorithm design and analysis; Digital video broadcasting; Integrated circuit interconnections; Iterative algorithms; Iterative decoding; Message passing; Parity check codes; Routing; Strontium; Wires;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1465805
