• DocumentCode
    3547606
  • Title

    A partial parallel algorithm and architecture for arithmetic encoder in JPEG2000

  • Author

    Li, Yijun ; Elgamel, Mohamed ; Bayoumi, Magdy

  • Author_Institution
    Center for Adv. Comput. Studies, Louisiana Univ., Lafayette, LA, USA
  • fYear
    2005
  • fDate
    23-26 May 2005
  • Firstpage
    5198
  • Abstract
    For JPEG2000 real-time applications, embedded block coding with optimized truncation (EBCOT) is a time-consuming part and becoming a bottleneck for the entire system throughput. Since the arithmetic encoder (AE) is one part of EBCOT, low performance of AE can significantly degrade the performance. AE is inherently a serial process with high dependency and parallelization of AE is difficult. In this paper, a partial parallel algorithm for AE is proposed. One distinct characteristic of the proposed algorithm is that two contexts can be processed in one clock cycle. Based on the proposed algorithm, a pipelined architecture is implemented. Experimental results, with standard test image benchmarks, show that the proposed algorithm and architecture achieves about 24% improvement in the system throughput in comparison with the architecture based on the original AE algorithm.
  • Keywords
    arithmetic codes; block codes; image coding; parallel architectures; pipeline processing; EBCOT; JPEG2000 real-time applications; arithmetic encoder; optimized truncation embedded block coding; partial parallel algorithm; pipelined architecture; single clock cycle dual context processing; system throughput improvement; Arithmetic; Clocks; Computer architecture; Digital cameras; Discrete wavelet transforms; Image coding; Parallel algorithms; Throughput; Tiles; Transform coding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
  • Print_ISBN
    0-7803-8834-8
  • Type

    conf

  • DOI
    10.1109/ISCAS.2005.1465806
  • Filename
    1465806