An efficient model for performance analysis of asynchronous pipeline design methods

In this paper, an efficient yet accurate model for extracting analytical expressions for throughput and latency of asynchronous pipeline styles is presented. The model is then applied to ten styles including GasP, MOUSETRAP, IPCMOS, LP_SR2/1, LP_HC, STFB, LDA, LP2/1, RSPCFB and NCL. The first five designs are based on the bundled-data (BD) category while the last five are based on the data-driven (DD) category. The performance of the styles are compared in terms of throughput, latency, power dissipation and transistor count. A figure of merit for the energy consumption and the performance is used to determine the better styles. The results of the analytical model are compared with (pre-layout) HSPICE simulation with a 0.18 μm CMOS technology revealing a very good accuracy for the proposed model.