Title :
A memory controller that reduces latency of cached SDRAM
Author :
Miura, Seiji ; Akiyama, Satoru
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
The proposed controller has two main control schemes, address-alignment control and dummy-cache control. These two schemes cooperatively control cached SDRAM to reduce its latency. Testing of the controller using benchmark programs demonstrated that latency was reduced 25% and execution time was reduced 13% compared to those of a sense-amplifier cache controller for standard SDRAM. The proposed controller requires 9.2 Kgates at a supply voltage of 1.8 V and an operating frequency of 133 MHz.
Keywords :
DRAM chips; cache storage; integrated circuit design; 1.8 V; 133 MHz; address-alignment control; benchmark programs; cached SDRAM latency reduction; dummy-cache control; memory controller; sense-amplifier cache controller; standard SDRAM; synchronous DRAM; Benchmark testing; Cache memory; Centralized control; Delay; Frequency; Laboratories; Operational amplifiers; Random access memory; SDRAM; Voltage control;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1465819
