A low-power scan-path architecture

In this paper, we propose a scan cell architecture that decreases power consumption and the total consumed energy. In the method, which is based on data compression, the test vector (TV) set is divided into two repeated and unrepeated partitions. The repeated part, which is common among some of the TVs, is not changed during the new scan path where the new TV will be filled. Therefore, every time that a new TV is applied to the circuit, only the cells of the scan-path which are not repeated are altered and other cells retain their values. As a result, the TV is applied to the CUT in a fewer number of clock cycles. In addition, the values of some scan cells remain unchanged leading to a lower switching activity in the scan-path during test mode. Besides, by latching the inputs of the CUT, the proposed scan chain architecture avoids transitioning of TVs into the circuit inputs at the time of shifting. This also saves system power during the test mode. Our architecture has been applied to ISCAS89 circuits. Simulation results reveal up to 66% reduction in the test power consumption when compared to the conventional scan-path architecture.