A re-configurable high-speed CMOS track and latch comparator with rail-to-rail input for IF digitization [software radio receiver applications]

A re-configurable high speed track and latch comparator with rail-to-rail input range is designed in a 0.18 μm CMOS process. The comparator architecture consists of parallel PMOS and NMOS differential pairs followed by a regenerative latch. The bias current of the differential pairs and the duty cycle of the clock can be adjusted so that the comparator consumes the minimum amount of power for a given input voltage sensitivity and a given clock frequency. The comparator is suitable as a building block for a re-configurable analog-to-digital converter in an IF digitizing software radio receiver.