DocumentCode
3547692
Title
On the implementation of 128-pt FFT/IFFT for high-performance WPAN
Author
Huggett, Clare ; Maharatna, Koushik ; Paul, Kolin
Author_Institution
Bristol Univ., UK
fYear
2005
fDate
23-26 May 2005
Firstpage
5513
Abstract
The paper deals with the efficient realization of a 128-pt FFT/IFFT processor for application in the IEEE 802.15.3a standard for wireless personal area networks (WPAN). The 128-pt FFT/IFFT architecture has been designed by devolving it into one 8-pt and one 16-pt FFT. The 16-pt FFT was decomposed again and two separate 128-pt FFT algorithms have been developed, viz., 8×4×4 and 8×2×8. Their relative merits and demerits have been analyzed from the algorithm and implementation points of view. The architectures have been prototyped on a Virtex II FPGA. The results indicate that the 8×2×8 architecture is better suited for the stated purpose.
Keywords
fast Fourier transforms; field programmable gate arrays; integrated circuit layout; personal area networks; signal processing; FFT; FFT/IFFT processor; IFFT; Virtex II FPGA; floorplan; high-performance WPAN; wireless personal area networks; Algorithm design and analysis; Computer architecture; Discrete Fourier transforms; Equations; Field programmable gate arrays; OFDM; Parallel processing; Physical layer; Proposals; Prototypes;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1465885
Filename
1465885
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