Automated design of a 10-bit, 80MSPS WLAN DAC for linearity and low-area

The paper presents the design of a 10-bit, 80 MSPS current steering D/A converter (DAC) using only digital thin-oxide CMOS transistors. A large part of the design is automated reducing the design cycle time. To combat systematic gradients on the wafer, we propose using global combinatorial optimization techniques such as simulated annealing and genetic algorithms to obtain a nearly optimal randomized array without any additional area penalty. Additionally, a simple yet elegant technique is used in the current-to-voltage conversion amplifier following the DAC to improve its phase margin in the presence of process variations without expending extra power. The DAC fabricated in a 0.13 micrometre digital CMOS technology shows an INL and DNL of 0.4 and 0.5 LSB respectively, an SFDR of greater than or equal to 70 dB, occupying 0.26 mm² and expending 1.25 mA static power.