A 12-B 10-msamples/s CMOS switched-current delta-sigma modulator

Author

Sung, Guo-Ming ; Chang, Kuo-Hsuan ; Lin, Wen-Sheng

Author_Institution

Dept. of Electr. Eng., Nat . onal Taipei Univ. of Technol., Taiwan

fYear

2005

fDate

23-26 May 2005

Firstpage

5573

Abstract

This paper presents the design of fully differential second-order delta-sigma modulator. A current feedback technique is used in the proposed switched-current feedback memory cell (FMC) to decrease the input impedance and to improve the transmission error in the memory cell. Furthermore, the entire memory cell is designed in a coupled differential replicate (CDR) form to eliminate the clock feedthrough (CFT) error. In this paper, the SDM is simulated with TSMC 0.35 micrometre CMOS process technology. The simulation results reveal that the peak signal to noise plus distortion ratio (SNDR) is 75 dB at 10.24 MHz sampling rate with 40 kHz bandwidth, and the power dissipation is 16 mW.

Keywords

CMOS integrated circuits; circuit feedback; delta-sigma modulation; switched current circuits; 10.24 MHz; 16 mW; 40 kHz; CMOS; TSMC; clock feedthrough error; coupled differential replicate form; current feedback; differential second-order delta-sigma modulator; feedback memory cell; input impedance; signal to noise plus distortion ratio; switched-current delta-sigma modulator; transmission error; CMOS process; CMOS technology; Clocks; Couplings; Delta modulation; Distortion; Feedback; Impedance; PSNR; Signal sampling; clock feedthrough error; delta-sigma modulator; memory cell; switched-current;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465900

Filename

1465900