DocumentCode
3547722
Title
A high-level dynamic-error model of a pipelined analog-to-digital converter
Author
Folkesson, Kalle ; Svensson, Christer ; Knuthammar, Björn ; Dreyfert, Andreas
Author_Institution
Dept. of Electr. Eng., Linkoping Univ., Sweden
fYear
2005
fDate
23-26 May 2005
Firstpage
5625
Abstract
The paper presents a fast and accurate high-level model of a pipelined analog-to-digital converter implemented in MATLAB. Mechanisms causing dynamic errors, such as the settling time of a slew-rate-limited amplifier, are analyzed and parameters to model these identified. All parameters are associated with actual physical properties and all simulations are validated by comparison to measured data in both time and frequency domains.
Keywords
CMOS integrated circuits; analogue-digital conversion; circuit simulation; integrated circuit modelling; CMOS process; MATLAB model; dynamic errors; frequency domain; high-level dynamic-error model; pipelined analog-to-digital converter; settling time; slew-rate-limited amplifier; time domain; Analog-digital conversion; Circuit simulation; Clocks; Error correction; Frequency domain analysis; MATLAB; Mathematical model; Sampling methods; Semiconductor device modeling; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1465913
Filename
1465913
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