Design of MOS current mode logic gates - computing the limits of voltage swing and bias current

Minimizing a quality metric for an MCML gate, such as power-delay product or energy-delay product, requires solving a system of nonlinear equations subject to constraints on both bias current and voltage swing. In this paper, we show that the limits of the swing and the bias current are affected by the constraints on maximum area and maximum delay. Moreover, methods for computing such limits are presented.