Interconnect delay optimization via high level re-synthesis after floorplanning

With the progress of manufacturing technologies, more transistors can be integrated into one chip, which validates the system-on-chip (SoC) technology. Besides, as the feature size of integrated circuits scales down into super deep sub-micron level, interconnect delay has played a dominant role in total delay of the circuit. A new technology which improves the performance of the circuit in high-level synthesis phase by utilizing high level re-synthesis after floorplan is presented in this paper. The techniques presented in this paper are demonstrated by experiments.