Title :
Validation analysis and test flow optimization of VLSI chip
Author :
Tan, Yanzhuo ; Han, Yinhe ; Li, Xiaowei ; Feiyin Lu ; Chen, Yuchuan
Author_Institution :
Inst. of Comput. Technol., Chinese Acad. of Sci., Beijing, China
Abstract :
This paper gives a validation analysis on a high-performance general-purpose processor, using the 0.18 μm process, and based on this analysis a test flow optimization algorithm is presented. The fault detection capacity of different test items is first analyzed. Then the validation information can be reused to generate a test item efficiency table. Based on this table, a tradeoff between test item efficiency and test time is achieved as the heuristic object for optimizing our test flow, which can save much test time of faulty chips. Compared to the dynamic programming algorithm, the complexity of our heuristic ordering algorithm has been decreased from O(dn2n) to O(dn3). Several experimental results have shown that this algorithm is efficient.
Keywords :
boundary scan testing; built-in self test; design for testability; greedy algorithms; heuristic programming; integrated circuit testing; logic testing; microprocessor chips; optimisation; 0.18 micron; BIST logic circuits; CPU chip; DFT techniques; VLSI chip validation analysis; at-speed test; dynamic programming algorithm; general-purpose processor; greedy heuristic ordering algorithm; item efficiency/test time tradeoff; scan chains; test flow optimization; test item efficiency table; test item fault detection capacity; Algorithm design and analysis; Automatic testing; Built-in self-test; Costs; Dynamic programming; Heuristic algorithms; Logic testing; Production; Test equipment; Very large scale integration; at-speed test; dynamic programming algorithm; heuristic ordering algorithm; validation analysis;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1465923
