Validation analysis and test flow optimization of VLSI chip

This paper gives a validation analysis on a high-performance general-purpose processor, using the 0.18 μm process, and based on this analysis a test flow optimization algorithm is presented. The fault detection capacity of different test items is first analyzed. Then the validation information can be reused to generate a test item efficiency table. Based on this table, a tradeoff between test item efficiency and test time is achieved as the heuristic object for optimizing our test flow, which can save much test time of faulty chips. Compared to the dynamic programming algorithm, the complexity of our heuristic ordering algorithm has been decreased from O(dn2ⁿ) to O(dn³). Several experimental results have shown that this algorithm is efficient.