Instruction-based delay fault self-testing of pipelined processor cores

Although nearly all modern processors use a pipelined architecture, no method has yet been proposed in the literature to model these for the purpose of test generation. The paper proposes a graph theoretic model of pipelined processors and develops a systematic approach for delay fault testing of such processor cores using the processor instruction set. Our methodology consists of using a graph model of the pipelined processor, extraction of architectural constraints, classification of paths, and generation of tests using a constrained ATPG. These tests are then converted to a test program, a sequence of instructions, for testing the processor. Thus, the tests generated by our method can be applied in a functional mode of operation and can also be used for self-test. We applied our method to two example processors, namely a 16 bit five stage VPRO pipelined processor and a 32 bit pipelined DLX processor, to demonstrate the effectiveness of our methodology.