Implementation of SIMD vision chip with 128×128 array of analogue processing elements

This paper presents the latest implementation of the SIMD current-mode analogue matrix processor architecture. The SCAMP-3 vision chip has been fabricated in a 0.35 micrometre CMOS technology and comprises a 128×128 general-purpose programmable processor-per-pixel array. The architecture of the chip is overviewed and implementation issues are considered. The circuit design of the analogue register is presented, the layout of the analogue processing element is discussed and the design of control-signal drivers and readout circuitry is overviewed.