Area-efficient systolic architectures for inversions over GF(2m)

Based on a new reformulation of the extended Euclidean algorithm, we propose two types of in-place systolic architectures for inversion in GF(2^m): bit-parallel and folded bit-parallel architectures. Our bit-parallel architectures have throughput of either 1/(2m-1) with interleaving or 1/(4m-2) without interleaving. Compared with the best previously proposed bit-parallel architectures of which we are aware, our new architectures require less hardware and achieve shorter critical path delays with approximately the same throughput and latency. We also propose a folded version of our bit-parallel architectures which achieves the 1/(4m-2) non-interleaved throughput with even less hardware. To our best knowledge, no comparable architecture has been proposed before.