Reconfigurable multiple scan-chains for reducing test application time of SOCs

We propose an algorithm, based on a framework of reconfigurable multiple scan-chains for a system-on-chip, to minimize test application time. For the framework, the control signal combination causes the computing time to increase exponentially. The algorithm we propose introduces a heuristic control signal selection method to solve this problem. We also minimize the test application time by using the balancing method to assign registers into multiple scan-chains. It could show significant reductions in test application times and computing times.