Title :
Designing and packaging technology of Renesas SIP
Author :
Sakamoto, Noriaki ; Sugita, Norihiko ; Kikuchi, Takafumi ; Tanaka, Hideki ; Akazawa, Takashi
Author_Institution :
Syst. Solution Integrated Product Design Dept, Renesas Technol. Corp, Tokyo, Japan
Abstract :
Renesas Technology Corp. started an SIP (solution integrated product) Project in April 1999, aiming at the promotion of the SiP (system in package) business. SiP can achieve 1/10-1/6 design TAT (turn around time) in comparison with SoC (system on chip). SiP, which packs a few chips in a single package, has also advantages of EMI noise reduction and customer´s substrate area reduction by using signal integrity analysis technology and packaging technology of a planar and a stack structure. On the basis of these technologies, we can enlarge SIP for the digital consumer field, analog included digital field, and other fields.
Keywords :
chip scale packaging; flip-chip devices; lead bonding; multichip modules; product design; system-on-chip; time to market; EMI noise reduction; Renesas Technology Corporation; SoC; analog included digital field; design technology; design turn around time; digital consumer field; flip chip bonding; packaging technology; planar structure; signal integrity analysis technology; solution integrated product; stack structure; substrate area reduction; system in package; system on chip; wire bonding; Acoustic noise; Costs; Digital cameras; Electromagnetic interference; Investments; Packaging; Product design; SDRAM; System-on-a-chip; Testing;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1465988
