Rules for systematic synthesis of all-transistor analogue circuits by admittance matrix expansion

A previous method for synthesis of all-transistor circuits suffered from the disadvantage that it generated a large number of possible circuits which would require computer generation and evaluation. We propose restrictions on the transformations used in the synthesis such that the number of circuits generated is much reduced while retaining circuits which have desirable performance characteristics. Finally, we consider reduction of the trial-and-error element in the synthesis process by exploring carrying out the synthesis entirely in the admittance matrix domain.