DocumentCode
3547824
Title
A cost-effective memory-based real-valued FFT and Hermitian symmetric IFFT processor for DMT-based wire-line transmission systems
Author
Chi, Hsiang-Feng ; Lai, Zhao-Hong
Author_Institution
Dept. of Commun. Eng., Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan
fYear
2005
fDate
23-26 May 2005
Firstpage
6006
Abstract
This paper presents an efficient computation scheme for the memory-based FFT/IFFT processor used in DMT (discrete multi-tone) systems. Only half-size FFT/IFFT is required to transform real-valued data and Hermitian symmetric data. That is, the cost in processing elements and memory can be reduced by two. Finally, a variable-size radix-4 memory-based FFT/IFFT processor with block scaling scheme is designed for DMT systems.
Keywords
Hermitian matrices; digital signal processing chips; fast Fourier transforms; floating point arithmetic; DMT-based wire-line transmission systems; Hermitian symmetric IFFT processor; block scaling; discrete multitone systems; half-size FFT/IFFT; memory-based processor architecture; real-valued FFT; reduced-complexity FFT/IFFT processor; variable-size radix-4 processor; Costs; Discrete Fourier transforms; Discrete transforms; Fast Fourier transforms; Hardware; Internet; OFDM modulation; Silicon; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1466008
Filename
1466008
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