A hardware-based predictive motion estimation algorithm

For low-power motion estimation hardware solutions, advanced hardware aimed algorithms and architectures are a necessity. A hardware solution for the modern emerging standard H.264 is investigated. Design trade-offs, including search patterns, predictors, and memory architecture, have been made with power consumption and hardware complexity in mind. The memory architecture has been optimised for the variable block sizes used in H.264 motion estimation. All predictors are refined with the small search pattern. An average PSNR of -0.0438 dB compared to the full-search algorithm was simulated. A 2.793 mm² layout, using 0.18 μm CMOS technology, of the design running at 7.61 MHz is presented.