Title :
A 4-bit 5 GS/s flash A/D converter in 0.18 μm CMOS
Author :
Sheikhaei, Samad ; Mirabbasi, Shahriar ; Ivanov, Andre
Author_Institution :
Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada
Abstract :
A 4-bit 5 GS/s flash analog-to-digital converter (ADC) is designed and simulated in a 0.18 μm CMOS technology. Low-swing operation both in the analog and the digital circuitry results in high-speed low power operation. The ADC dissipates 70 mW power from a 1.8 V supply while operating at 5 GHz. Offset averaging is used to minimize the effect of comparator offsets. Simulation results show that offset voltages with 67 mV standard deviation (i.e., 1 LSB) can be tolerated. Static INL and DNL errors are 0.34 LSB and 0.24 LSB respectively, and the ENOB is 3.65 bits. The simulation results of this non-time-interleaved flash ADC demonstrates a significant improvement in terms of power and area compared to those of previously reported ADCs.
Keywords :
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); low-power electronics; 0.18 micron; 1.8 V; 5 GHz; 70 mW; ADC; CMOS; ENOB; comparator offset effect minimization; flash A/D converter; high-speed low power operation; low-swing operation; nontime-interleaved flash ADC; offset averaging; static DNL errors; static INL errors; Analog-digital conversion; CMOS technology; Calibration; Circuit simulation; Laser radar; Latches; Resistors; Sampling methods; Signal generators; Voltage;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1466041