Title :
An 8-bit 160 MS/s folding-interpolating ADC with optimized active averaging/interpolating network
Author :
Azin, Meysam ; Movahedian, Hamid ; Bakhtiar, Mehrdad Sharif
Author_Institution :
Dept. of Electr. Eng., Sharif Univ. of Technol., Tehran, Iran
Abstract :
An 8-bit CMOS folding-interpolating analog-to-digital converter is presented. A new method for designing an optimized averaging circuit is also described. Careful circuit design and layout leads to a high-speed (160 MSPS) and low power (70 mW in 2.5 V supply voltage) ADC. The ADC is successfully implemented in 0.25 μm CMOS digital process and it takes 1×1.4 mm2 silicon area.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; circuit optimisation; low-power electronics; 0.25 micron; 2.5 V; 70 mW; 8 bit; CMOS digital process; analog-to-digital converter; circuit layout; folding-interpolating ADC; high-speed ADC; low power ADC; optimized active averaging/interpolating network; CMOS technology; Circuits; Delay; Design methodology; Error correction; Interpolation; Pipelines; Resistors; Signal generators; Signal sampling;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1466044
