Title :
A 12 bits/200 MHz resolution/sampling/power-optimized ADC in 0.25 μm SiGe BiCMOS
Author :
Wu, Q. ; Wang, A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA
Abstract :
Design of a resolution/sampling-rate/power-optimized analog-to-digital converter (ADC) in a foundry 0.25 μm SiGe BiCMOS for digital communications is presented. It is based on a combined four-stage multi-bit pipelined, subranging and interpolating architecture with novel digital correction technique. The expanded subranging structure along with the proposed multiple MDAC (multiplying DAC) and relative comparison method used in sub ADC simplifies the 2nd and 3rd stages. The ADC features 12 bit resolution, 200 MHz sampling rate, differential nonlinearity (DNL) of ±0.6 LSB, integral nonlinearity (INL) of ±1.1 LSB, power dissipation of 380 mW and a die size of 6 mm2.
Keywords :
BiCMOS integrated circuits; Ge-Si alloys; analogue-digital conversion; circuit optimisation; digital communication; digital-analogue conversion; multiplying circuits; pipeline processing; 0.25 micron; 12 bit; 200 MHz; 380 mW; BiCMOS; Ge-Si; SiGe; analog-to-digital converter; digital communications; digital correction; four-stage multi-bit pipelined architecture; interpolating architecture; multiple MDAC; multiplying DAC; power-optimized ADC; relative comparison method; resolution-optimized ADC; sampling-optimized ADC; subranging architecture; Bandwidth; BiCMOS integrated circuits; Capacitors; Germanium silicon alloys; Interpolation; Nonlinear distortion; Resistors; Sampling methods; Silicon germanium; Voltage;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1466050
