The realization of a mismatch-free and 1.5-bit over-sampling pipelined ADC

This paper proposes a simple method to realize an over-sampling pipelined analog-to-digital converter (ADC) with 1.5-bit bit-blocks. The ADC performs conversion by permuting internal capacitors in alternate clocks of the upper 1.5-bit bit-blocks in the analog domain, then averaging the data from bit-blocks in the digital domain. The behavioral simulation of a 14-bit ADC verified that this over-sampling pipelined ADC with 1.5-bit bit-blocks has more than 70 dB of spurious-free dynamic range (SFDR) for up to an 8 MHz input signal when each of the upper three bit-blocks has a gain error of +0.8 %. Using a S/H circuit in front improves the SFDR to 95 dB up to the signal frequency bandwidth of 25.6 MHz when the clock frequency is 102.4 MHz.