Title :
A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation
Author :
Li, Zhuoyuan ; Hong, Xianlong ; Zhou, Qiang ; Cai, Yici ; Bian, Jinian ; Yang, Hannal ; Saxena, Prashant ; Pitchumani, Vijay
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
An efficient and effective divide-and conquer 2.5D floorplanning algorithm is proposed for wirelength optimization. Modules are pre-partitioned into different dies with respect to the statistical wirelength estimation result. Then a floorplan is generated on each die for wirelength optimization. The new partitioning method successfully solves the conflict between wirelength minimization and inter-die via constraints. Experimental results show that our algorithm could provide noticeable improvement in the total wirelength compared to both 2D design and the previous 2.5D floorplanning algorithm.
Keywords :
circuit layout; circuit optimisation; divide and conquer methods; 2.5D floorplanning algorithm; divide-and-conquer algorithm; inter-die via constraints; partitioning; statistical wirelength estimation; wirelength optimization; Algorithm design and analysis; Computer science; Costs; Delay; Integrated circuit interconnections; Manufacturing; Minimization methods; Partitioning algorithms; Very large scale integration; Wire;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1466064
