A fast convergence and area-efficient decoder for quasi-cyclic low-density parity-check codes

The quasi-cyclic low-density parity-check (QC-LDPC) codes have attracted much attention in space communication systems. However, the decoders are still difficult to be applied in practice for their large area and high memory requirements. Moreover, the clock cycles for the input and output interfaces can not be ignored due to the I/O resource is also limited on this occasion, which influences the throughput improvement significantly. This paper presents a parallel pipelined decoder architecture for QC-LDPC codes, which can largely reduce their area and memory size while maintaining a fast convergence speed. The decoding approach reformulates the original normalized min-sum algorithm and adopts a two pipelines architecture to eliminate the clock cycles for the I/O and reduce the number of clock cycles per iteration. Chip designed with TSMC 0.13-μm eight-metal-layer standard CMOS technology shows that it can achieve a throughput up to 767 Mbps with only 3.12 mm² core area consumption. Especially, only 36 I/O ports are occupied, less than 10% of the conventional decoders.