Effective analytical delay model for transistor sizing

This paper describes an analytical delay model for transistor sizing. Two primitives are selected to be mapped for computing gate delay. These primitives model the short-channel effect and body effect in deep submicron CMOS circuits. A mapping algorithm for arbitrary serial-parallel structures is adopted. The delay of complex gates using such mappings to primitives is found to be within 10% of SPICE for most of the gates. The delay model is incorporated into a transistor sizing algorithm based on TILOS. Also presented are the experimental results for several circuits from LGSynth91 benchmark suite.