Title :
Effective analytical delay model for transistor sizing
Author :
Wo, Zhaojun ; Koren, Israel
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
This paper describes an analytical delay model for transistor sizing. Two primitives are selected to be mapped for computing gate delay. These primitives model the short-channel effect and body effect in deep submicron CMOS circuits. A mapping algorithm for arbitrary serial-parallel structures is adopted. The delay of complex gates using such mappings to primitives is found to be within 10% of SPICE for most of the gates. The delay model is incorporated into a transistor sizing algorithm based on TILOS. Also presented are the experimental results for several circuits from LGSynth91 benchmark suite.
Keywords :
CMOS integrated circuits; SPICE; integrated circuit modelling; LGSynth91 benchmark suite; SPICE; TILOS; analytical delay model; body effect; deep submicron CMOS circuits; gate delay; mapping algorithm; serial-parallel structures; short-channel effect; transistor sizing; Analytical models; Circuits; Delay effects; Delay estimation; Electronic mail; Packaging; SPICE; Semiconductor device modeling; Timing; Transistors;
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
DOI :
10.1109/ASPDAC.2005.1466194
