Low-leakage robust SRAM cell design for sub-100nm technologies

A novel low-leakage robust SRAM design for sub-100nm technologies, Hybrid SRAM (HSRAM) cell, is presented in this paper. Leakage power, especially subthreshold leakage and gate leakage, and soft error are challenging the design of SRAM. While these important issues have been separately addressed in previous SRAM designs, there exists no design that simultaneously cuts down leakage power and enhances the resistance to soft error. In this work, we have built the first such SRAM cell, by hybrid of high-κ gate dielectric and dynamic threshold voltage which is realized in the form of jointly biased gate and substrate transistor. The HSRAM not only makes the gate leakage negligible, but lessens the severe increase of subthreshold leakage caused by Fringing/Field Induced Barrier Lowering (FIBL) effect accompanied with the introduction of high-κ gate dielectric, and in the same time reduces the susceptibility to soft error by increasing the node capacitance. Experiments were performed in both transistor level and circuit level for this novel HSRAM using ISE8.0 and HSPICE. They indicate that up to 93% reduction in total leakage is possible by using HSRAM cell, with an up to 23% increase in reliability degree and an up to 73% reduction in bitline delay, compared to standard 6T SRAM.