Title :
Phase-locked loop synthesis using hierarchical divide-and-conquer multi-optimization
Author :
Chu, Min ; Allstot, David J.
Author_Institution :
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
Abstract :
A hierarchical divide-and-conquer multi-optimization methodology for phase-locked loop synthesis is presented. By optimizing each building block in the PLL separately with various optimization techniques, high optimization efficiency and good circuit performance are achieved. The methodology is validated with the synthesis of a 1GHz third-order PLL in 240nm SiGe BiCMOS.
Keywords :
BiCMOS integrated circuits; Ge-Si alloys; circuit analysis computing; circuit optimisation; divide and conquer methods; phase locked loops; 1 GHz; 240 nm; BiCMOS; SiGe; circuit optimization; hierarchical divide-and-conquer multi-optimization; phase-locked loop synthesis; Circuit optimization; Circuit synthesis; Clocks; Frequency conversion; Frequency synthesizers; Phase frequency detector; Phase locked loops; Phase noise; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
DOI :
10.1109/ASPDAC.2005.1466418
