DocumentCode :
3548324
Title :
Constructing zero-deficiency parallel prefix adder of minimum depth
Author :
Zhu, Haikun ; Cheng, Chung-Kuan ; Graham, Ronald
Author_Institution :
Dept. of Comput. Sci. & Eng., UCSD, La Jolla, CA, USA
Volume :
2
fYear :
2005
fDate :
18-21 Jan. 2005
Firstpage :
883
Abstract :
Parallel prefix adder is a general technique for speeding up binary addition. In unit delay model, we denote the size and depth of an n-bit prefix adder C(n) as sC(n) and dC(n) respectively. Snir proved that sC(n) +dC(n) > 2n - 2 holds for arbitrary prefix adders. Hence, a prefix adder is said to be of zero-deficiency if sC(n) + dC(n) = 2n - 2, In this paper, we first propose a new architecture of zero-deficiency prefix adder dubbed Z(d), which provably has the minimal depth among all kinds of zero-deficiency prefix adders. We then design a 64-bit prefix adder Z64, which is derived from Z(d)|d=8, and compare it against several classical prefix adders of the same bit width in terms of area and delay using logical effort method. The result shows that the proposed Z(d) adder is also promising in practical VLSI design.
Keywords :
adders; circuit CAD; integrated circuit design; logic CAD; parallel architectures; 64 bit; Z64 prefix adder; binary addition; logical effort method; minimal depth; n-bit prefix adder; zero-deficiency parallel prefix adder; Added delay; Adders; Arithmetic; Circuits; Computer science; Concurrent computing; Signal design; Timing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
Type :
conf
DOI :
10.1109/ASPDAC.2005.1466481
Filename :
1466481
Link To Document :
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