Area-IO DRAM/logic integration with system-in-a-package (SiP)

Author

Wang, A.M. ; Dai, Wayne

Author_Institution

Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA

Volume

2

fYear

2005

fDate

18-21 Jan. 2005

Firstpage

893

Abstract

This paper presents a cost-effective area-IO DRAM (aDRAM)/logic integration implemented with CLC (chip-laminate-chip)-based system-in-a-package (SiP) technology. By inserting 512 area-IOs into the area-IO DRAM, the bandwidth of the area-IO DRAM can achieve 10GB/s when working under 166MHz. An interface module with configurable IO width was also developed to make this implementation platform able to be adapted by various applications. A performance analysis, including bandwidth and power is also presented in this paper. It is demonstrated that area-IO DRAM/logic integration with SiP technology provides significant cost-effective implementation methodology compared with embedded DRAM and off-chip DRAM.

Keywords

DRAM chips; VHF circuits; chip scale packaging; circuit CAD; integrated circuit design; logic CAD; 10 GByte/s; 166 MHz; CLC-based system-in-a-package technology; SiP technology; aDRAM; chip-laminate-chip; configurable IO width; cost-effective area-IO DRAM; interface module; logic integration; Bandwidth; CMOS integrated circuits; CMOS logic circuits; CMOS technology; Costs; Fabrication; Graphics; Laminates; Performance analysis; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific

Print_ISBN

0-7803-8736-8

Type

conf

DOI

10.1109/ASPDAC.2005.1466483

Filename

1466483