DocumentCode
3548353
Title
A fault-tolerant FFT processor
Author
Tsunoyama, M. ; Naito, S.
Author_Institution
Nagaoka Coll. of Technol., Niigata, Japan
fYear
1991
fDate
25-27 June 1991
Firstpage
128
Lastpage
135
Abstract
A scheme for concurrent fault detection by recomputing and a fault-tolerant FFT processor using the scheme are proposed. An FFT processor with perfect shuffle is considered. The realization of the processor is based on a linear cellular automaton (LCA) model having the constant-weight and equidistance properties. When a fault occurs in the processor, the fault is detected concurrently and the processor is reconfigured by replacing the faulty butterfly unit with a normal one according to the state of the processor. The reconfiguration can be made within a clock period by making a state transition based on the LCA model and by reconnecting the butterfly units according to the new state. The processor can be reconfigured quickly, so that it can be used for highly reliable real-time data processing systems.<>
Keywords
computerised signal processing; digital signal processing chips; fast Fourier transforms; fault tolerant computing; finite automata; concurrent fault detection; constant-weight; equidistance properties; fault-tolerant FFT processor; faulty butterfly unit; highly reliable real-time data processing systems; linear cellular automaton; perfect shuffle; reconfiguration; state transition; Clocks; Data processing; Discrete Fourier transforms; Educational institutions; Fast Fourier transforms; Fault detection; Fault tolerance; Power system modeling; Power system reliability; Real time systems;
fLanguage
English
Publisher
ieee
Conference_Titel
Fault-Tolerant Computing, 1991. FTCS-21. Digest of Papers., Twenty-First International Symposium
Conference_Location
Montreal, Quebec, Canada
Print_ISBN
0-8186-2150-8
Type
conf
DOI
10.1109/FTCS.1991.146651
Filename
146651
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