Priority directed test generation for functional verification using neural networks

Functional verification is the bottleneck in delivering today´s highly integrated electronic systems and chips. We should notice the simulation times and computation resource challenge in the automatic pseudo-random test generation and a novel solution named priority directed test generation (PDG) is proposed in this paper. With PDG, a test vector which hasn´t been simulated is granted a priority attribute. The priority indicates the possibility of detecting new bugs by simulating this vector. We show how to apply artificial neural networks (ANNs) learning algorithm to the PDG problem. Several experiments are given to exhibit how to achieve better result in this PDG method.