DocumentCode :
3548371
Title :
On-chip thermal gradient analysis and temperature flattening for SoC design
Author :
Sato, Takashi ; Ichimiya, Junji ; Ono, Nobuto ; Hachiya, Kotaro ; Hashimoto, Mime
Volume :
2
fYear :
2005
fDate :
18-21 Jan. 2005
Firstpage :
1074
Abstract :
This paper quantitatively analyzes thermal gradient of SoC and proposes a thermal flattening procedure. First, the impact of dominant parameters, such as area occupancy of memory/logic, power density, and floorplan on thermal gradient and clock skew are studied. Important results obtained here are 1) the maximum temperature difference increases with higher memory area occupancy and 2) the difference is very floorplan sensitive. Then, we propose a procedure to amend thermal gradient. A slight floorplan modification using the proposed procedure improves on-chip thermal gradient significantly.
Keywords :
circuit analysis computing; system-on-chip; thermal analysis; SoC design; clock skew; memory/logic area occupancy; on-chip thermal gradient analysis; power density; temperature flattening; Clocks; Electronic packaging thermal management; Rapid thermal processing; System-on-a-chip; Temperature distribution; Temperature sensors; Thermal management; Thermal resistance; Timing; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
Type :
conf
DOI :
10.1109/ASPDAC.2005.1466526
Filename :
1466526
Link To Document :
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