DocumentCode :
3548380
Title :
Congestion prediction in floorplanning
Author :
Sham, Chiu-Wing ; Young, Evangeline E Y
Author_Institution :
Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, China
Volume :
2
fYear :
2005
fDate :
18-21 Jan. 2005
Firstpage :
1107
Abstract :
Routability optimization has become the major concern in floorplanning. In traditional floor planners, area minimization is an important issue. Due to the recent advances in VLSI technology, interconnect has become a dominant factor to the overall performance of a circuit. Routability prediction is thus very important in the floorplanning stage. In this paper, we propose a new congestion model to predict the congestion after detailed routing which is not confined to the assumption of shortest Manhattan distance routes. We have compared our new models and some existing models with the actual congestion measures obtained by global routing some placement results (using the Capo placer as stated in A. E. Caldwell et al. (2000)) with a publicly available maze router. Results show that our models can make significant improvement in estimation accuracy over the other models.
Keywords :
VLSI; circuit optimisation; network routing; VLSI technology; area minimization; congestion prediction; estimation accuracy improvement; global routing; maze router; routability optimization; shortest Manhattan distance routes; Computer science; Design optimization; Integrated circuit interconnections; Prediction methods; Predictive models; Routing; Shape; Tiles; Very large scale integration; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
Type :
conf
DOI :
10.1109/ASPDAC.2005.1466534
Filename :
1466534
Link To Document :
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