DocumentCode
3548385
Title
Placement for configurable dataflow architecture
Author
Ekpanyapong, Mongkol ; Healy, Michael ; Lim, Sung Kyu
Author_Institution
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Volume
2
fYear
2005
fDate
18-21 Jan. 2005
Firstpage
1127
Abstract
As wire delay increasingly becomes a significant performance bottleneck in monolithic architectures, there is a strong motivation to move to dataflow architectures. In this paper, we propose a set of placement algorithms for generic dataflow architectures. Our timing-driven and profile-driven placement algorithms respectively are targeting streaming and non-streaming applications. Compared to the conventional wirelength-driven algorithm, our timing-driven placer reduces the longest path delay by 23% and maximum slack by 26% at the cost of 10% increase in wirelength for streaming applications. In addition, our profile-driven placer reduces the total execution time of non-streaming applications by 17%. Lastly, our simultaneous timing/profile-driven placer reduces the total execution time of non-streaming applications by 13% on average.
Keywords
data flow computing; integrated circuit layout; monolithic integrated circuits; configurable dataflow architecture; generic dataflow architectures; monolithic architectures; non-streaming applications; placement algorithms; profile-driven placement; streaming applications; timing-driven placement; wire delay; wirelength-driven algorithm; Arithmetic; Computer architecture; Costs; Data engineering; Delay; Fabrics; Hardware; Parallel processing; Timing; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN
0-7803-8736-8
Type
conf
DOI
10.1109/ASPDAC.2005.1466539
Filename
1466539
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