DocumentCode
3548389
Title
Placement stability metrics
Author
Alpert, Charles J. ; Nam, Gi-Joon ; Villarribua, Paul ; Yildiz, Mehmet C.
Author_Institution
IBM Corp., Austin, TX, USA
Volume
2
fYear
2005
fDate
18-21 Jan. 2005
Firstpage
1144
Abstract
To achieve timing closure, one often has to run through several iterations of physical synthesis flows, for which placement is a critical step. During these iterations, one hopes to consistently move towards design convergence. A placement algorithm that is "stable" consistently drives towards similar solutions, even with changes in the input netlist and placement parameters. Indeed, the stability of the algorithm is arguably as important a characteristic as the wirelength it achieves. However, currently there is no way to actually quantify the stability of a placement algorithm. This work seeks to address the issue by proposing metrics that measure the stability of a placement algorithm. Our experimental results examine the stability of three different placement algorithms with our proposed metrics and convincingly illustrate that some algorithms are quantifiably more stable than others. We believe that this opens the door to applying different standards for evaluating placement algorithms in terms of their effectiveness for achieving timing closure.
Keywords
circuit stability; integrated circuit design; integrated circuit measurement; design convergence; input netlist; placement algorithm; placement parameters; placement stability metrics; timing closure; Algorithm design and analysis; Assembly; Convergence; Logic design; Logic gates; Partitioning algorithms; Routing; Simulated annealing; Stability; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN
0-7803-8736-8
Type
conf
DOI
10.1109/ASPDAC.2005.1466543
Filename
1466543
Link To Document