• DocumentCode
    3548390
  • Title

    Redundant-via enhanced maze routing for yield improvement

  • Author

    Gang Xu ; Huang, Li-Da ; Pan, David Z. ; Wong, Martin D F

  • Author_Institution
    Dept. of CS, Texas Univ., Austin, TX, USA
  • Volume
    2
  • fYear
    2005
  • fDate
    18-21 Jan. 2005
  • Firstpage
    1148
  • Abstract
    Redundant via insertion is a good solution to reduce the yield loss by via failure. However, the existing methods are all post-layout optimizations that insert redundant via after detailed routing. In this paper, we propose the first routing algorithm that considers feasibility of redundant via insertion in the detailed routing stage. Our routing problem is formulated as maze routing with redundant via constraints. The problem is transformed to a multiple constraint shortest path problem, and solved by Lagrangian relaxation technique. Experimental results show that our algorithm can find routing layout with much higher rate of redundant via than conventional maze routing.
  • Keywords
    integrated circuit layout; integrated circuit yield; network routing; redundancy; Lagrangian relaxation technique; multiple constraint shortest path problem; post-layout optimizations; redundant via insertion; redundant-via enhanced maze routing; routing algorithm; routing layout; via failure; yield improvement; Delay; Design for manufacture; Electronic design automation and methodology; Manufacturing; Optimization methods; Routing; Shortest path problem; Thermal stresses; Very large scale integration; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
  • Print_ISBN
    0-7803-8736-8
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2005.1466544
  • Filename
    1466544