DocumentCode :
3548391
Title :
Interconnect estimation without packing via ACG floorplans
Author :
Wang, Jia ; Zhou, Hai
Author_Institution :
Dept. of ECE, Northwestern Univ., Evanston, IL, USA
Volume :
2
fYear :
2005
fDate :
18-21 Jan. 2005
Firstpage :
1152
Abstract :
ACG (adjacent constraint graph) is a general floorplan representation. The refinement of constraint graphs gives not only an efficient representation but also a representation sharing the advantage of adjacency graphs. As most edges in an ACG are between modules that are close to each other, the physical-distance of two modules can be measured without packing by the shortest path between them on the ACG. Experimental results verified this relationship and possible approaches for interconnect planning are discussed.
Keywords :
graph theory; integrated circuit design; integrated circuit interconnections; ACG floorplans; adjacency graphs; adjacent constraint graph; constraint graphs; floorplan representation; interconnect estimation without packing; interconnect planning; Binary sequences; Bridges; Compaction; Educational institutions; Geometry; Iterative algorithms; Iterative methods; Modular construction; Simulated annealing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
Type :
conf
DOI :
10.1109/ASPDAC.2005.1466545
Filename :
1466545
Link To Document :
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