DocumentCode
3548394
Title
Improving the scalability of SAMBA bus architecture
Author
Lu, Ruibing ; Cao, Aiqun ; Koh, Cheng-Kok
Author_Institution
Synopsys Inc., Mountain View, CA, USA
Volume
2
fYear
2005
fDate
18-21 Jan. 2005
Firstpage
1164
Abstract
SAMBA bus (Lu and Koh, 2003) is a high performance bus architecture that can deliver multiple transactions in one bus cycle under single-winner bus arbitration. The bus architecture displays several advantages such as, high bandwidth, low latency, and low performance penalty from arbitration delay, all of which make it more scalable than traditional buses. However, its scalability may be limited by the bus access logic delay. As a module is connected to the bus through its interface unit, which is connected in series on the bus, the bus logic delay increases linearly as the bus size increases. In this paper, we propose to increase the scalability of SAMBA buses through two methods: control signal lookahead and module clustering. The control signal lookahead technique can determine the bus access control signal in advance, thereby reducing the effective delay of each interface unit. Module clustering, on the other hand, can reduce the number of interface units attached to a bus. Experimental results show that combining these two methods can effectively reduce the bus logic delay, and thus increase the scalability of SAMBA buses.
Keywords
delays; integrated circuit design; system buses; system-on-chip; SAMBA bus; bus access control signal; bus access logic delay; bus architecture; bus scalability; bus size; control signal lookahead; module clustering; multiple transactions; single-winner bus arbitration; Access control; Bandwidth; Circuit testing; Delay effects; Delay lines; Displays; Logic; Multiplexing; Scalability; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN
0-7803-8736-8
Type
conf
DOI
10.1109/ASPDAC.2005.1466548
Filename
1466548
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