A fractional delay-locked loop for on chip clock generation applications

A fractional multiplying delay-locked loop (FMDLL) for high-speed on-chip clock generation applications is presented. The proposed DLL architecture overcomes some drawbacks of phase-locked loops (PLLs) such as jitter accumulation and stability while maintaining the advantageous of a PLL as a multi-rate fractional frequency multiplier. The output frequency range can be tuned from 1GHz to 2.5GHz with selectable multiplication ratios of M + 0.05 × AT where 1 ≥ K ≥ 19. To generate some finer ratios, K could be changed between two consecutive integer numbers. In this situation, a digital delta-sigma modulator could be used to suppress the spurs existing in the output spectrum.