A design of high speed double precision floating point adder using macro modules

Author

Huang, Chi ; Wu, Xinyu ; Lai, Jinmei ; Sun, Chengshou ; Li, Gang

Author_Institution

Microelectron., Fudan Univ., Shanghai, China

Volume

2

fYear

2005

fDate

18-21 Jan. 2005

Abstract

Based on SMIC 0.18μim 1.8V six-layer-metal CMOS process, we implement a 64-bit high speed pipelined floating point adder which satisfied IEEE 754 standard. After the critical path analysis of the pipelined structure, we custom design three macro modules in order to reduce critical path delay. After placement in datapath style and routing, we implement the layout of floating point adder. The chip area is 1.44 mm² and clock frequency is 518MHz.

Keywords

CMOS logic circuits; adders; circuit CAD; floating point arithmetic; high-speed integrated circuits; integrated circuit layout; logic CAD; network routing; pipeline arithmetic; 0.18 micron; 1.8 V; 518 MHz; 64 bit; SMIC six-layer-metal CMOS process; critical path analysis; critical path delay reduction; datapath style placement; floating point adder layout; high speed double precision floating point adder; high speed pipelined floating point adder; macro modules; routing; Acceleration; Adders; Capacitance; Circuit synthesis; Clocks; Delay; Frequency; Inverters; Routing; Software libraries;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific

Print_ISBN

0-7803-8736-8

Type

conf

DOI

10.1109/ASPDAC.2005.1466603

Filename

1466603