A low-power video segmentation LSI with boundary-active-only architecture

Author

Morimoto, Takashi ; Kiriyama, Osamu ; Adachi, Hidekazu ; Zhu, Zhaomin ; Koide, Tetsushi ; Mattausch, Hans Jurgen

Author_Institution

Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan

Volume

2

fYear

2005

fDate

18-21 Jan. 2005

Abstract

We designed a cell-network-based video segmentation test-chip in 0.35μm CMOS technology including a power reduction technique which activates only boundary cells of currently grown regions. The effectiveness of the proposed technique is confirmed by measurement results for a 41×33-sized cell-network, with 23μsec segmentation time (avg.) and 45.8mW power-dissipation (avg.) at 10MHz clock frequency.

Keywords

CMOS digital integrated circuits; digital signal processing chips; image segmentation; large scale integration; low-power electronics; video signal processing; 0.35 micron; 10 MHz; 23 mus; 41×33-sized cell-network; 45.8 mW; CMOS technology; boundary cells; boundary-active-only architecture; cell-network-based video segmentation test-chip; low-power video segmentation LSI; power reduction technique; CMOS technology; Circuit testing; Clocks; Frequency measurement; Hardware; Image segmentation; Large scale integration; Signal processing algorithms; System testing; Time measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific

Print_ISBN

0-7803-8736-8

Type

conf

DOI

10.1109/ASPDAC.2005.1466604

Filename

1466604