Title :
An improved test access mechanism structure and optimization technique in system-on-chip
Author :
Jianhua, Feng ; Long Jieyi ; Wenhua, Xu ; Hongfei, Ye
Author_Institution :
Dept. of Microelectron., Peking Univ., Beijing, China
Abstract :
This paper presents a new test access mechanism (TAM) architecture and optimization method based on an improved flexible-width test bus. The method is first to set up the test time lower bound that is not depends on TAM architecture, then to construct a bus assignment that makes test time up to the lower bound. We present experimental results on our improved flexible-width test buses for four benchmark SOCs. Experiment results in a significant reduction of the test time, and is better than the proposed traditional methods in test time.
Keywords :
automatic test pattern generation; circuit analysis computing; circuit optimisation; integrated circuit testing; logic testing; system-on-chip; TAM architecture; bus assignment; flexible-width test bus; optimization technique; system-on-chip; test access mechanism architecture; Benchmark testing; Clocks; Hip; Logic testing; Microelectronics; Optimization methods; Pins; System buses; System testing; System-on-a-chip;
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
DOI :
10.1109/ASPDAC.2005.1466609
