DocumentCode
3548492
Title
Fault-tolerant gamma interconnection networks
Author
Tzeng, N.-F. ; Chuang, P.-J.
Author_Institution
Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
fYear
1991
fDate
25-27 June 1991
Firstpage
282
Lastpage
289
Abstract
Modifications to the gamma interconnection network (GIN), which is composed of 3*3 basic building blocks, with interconnecting patterns between stages following the plus-minus-2/sup i/ functions, are discussed. The gamma network is modified by altering the interconnecting patterns between stages so as to create totally disjoint paths from any source (S) to any destination (D), ensuring high terminal reliability between every (S, D) pair. The network is called fault-tolerant GIN (FTGIN) since it can tolerate an arbitrary single fault. If several building blocks (i.e. 3*3 switches) are fabricated in one VLSI chip, the layout area and pin count are smaller for the FTGIN than for its GIN counterpart as a result of the change in the interconnection patterns, offering potential cost reduction. A lower bound on the terminal reliability of the FTGIN is derived, showing significant terminal reliability improvement over the conventional gamma network.<>
Keywords
fault tolerant computing; multiprocessor interconnection networks; VLSI chip; building blocks; destination; disjoint paths; fault tolerant gamma interconnection networks; interconnecting patterns; layout area; pin count; plus-minus-2/sup i/ functions; source; switches; terminal reliability; Communication switching; Computer network reliability; Computer networks; Costs; Fault tolerance; Hardware; Multiprocessing systems; Multiprocessor interconnection networks; Routing; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Fault-Tolerant Computing, 1991. FTCS-21. Digest of Papers., Twenty-First International Symposium
Conference_Location
Montreal, Quebec, Canada
Print_ISBN
0-8186-2150-8
Type
conf
DOI
10.1109/FTCS.1991.146674
Filename
146674
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